FIFO configuration register
| RXFIFO_WM_THRHD | The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid. |
| TXFIFO_WM_THRHD | The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid. |
| NONFIFO_EN | Set this bit to enable APB non-FIFO mode. |
| FIFO_ADDR_CFG_EN | When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. |
| RX_FIFO_RST | Set this bit to reset RX FIFO. |
| TX_FIFO_RST | Set this bit to reset TX FIFO. |
| NONFIFO_RX_THRES | When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data. |
| NONFIFO_TX_THRES | When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data. |
| FIFO_PRT_EN | The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty. |